In semiconductor devices, a metal interconnection may be connected to an upper portion of a metal line formed on a semiconductor substrate, and may apply an electric signal to a semiconductor device. Such connection may be achieved through a contact hole.
In a multi-layered interconnection structure, metal interconnection layers and insulating layers may alternately be formed on the semiconductor substrate. Metal interconnection layers, which may be isolated from each other by the insulating layers, may be electrically connected to each other, for example through via holes so that circuits can be operated.
A related art method of forming a metal interconnection of a semiconductor device will be described with reference to accompanying drawings.
FIGS. 1A to 1F are example sectional diagrams illustrating a related art procedure for forming the metal interconnection of a semiconductor device.
Referring to FIG. 1A, first metal line 4 may be formed on semiconductor substrate 2 including a structure (not shown) formed through a known semiconductor manufacturing process. Pre-metal dielectric (PMD) layer 6 may be formed on a surface, for example the entire top surface, of semiconductor substrate 2 including first metal line 4. PMD layer 6 may be planarized, for example through a chemical mechanical polishing (CMP) process.
Referring to FIG. 1B, a photoresist film may be coated on PMD layer 6, and then subjected to an exposure and development process. Photoresist film pattern 8 that may expose a prescribed portion of PMD layer 6 may thereby be formed.
Referring to FIG. 1C, exposed PMD layer 6 may be dry-etched by, for example using photoresist film pattern 8 as a mask. Contact hole 10 may thereby be formed, which may expose a part of metal line 4. Photoresist layer pattern 8 may then be removed.
Referring to FIG. 1D, barrier metal layer 12 may be shallowly deposited on an entire surface of a PMD layer 6a including an inner wall of contact hole 10. Metal layer 14 may be formed on barrier metal layer 12 in such a manner that contact hole 10 may be filled with metal layer 14.
Referring to FIG. 1E, barrier metal layer 12 and metal layer 14 may be planarized through the CMP process until a surface of PMD layer 6a is exposed.
Referring to FIG. 1F, second metal line pattern 16 may be formed on PMD layer 6a, barrier metal layer 12a, and metal layer 14a. The metal interconnection of a semiconductor device may thereby be formed.
A related art semiconductor and related methods may have various problems. For example, when forming a metal interconnection of the semiconductor device according to the related art, since the metal interconnection of the semiconductor device may be formed according to a predetermined design, a number of metal interconnections may need to be increased to operate the semiconductor device under a high voltage level as may be required by a user. Such an increase of the metal interconnections may raise a failure rate of a semiconductor device.
In addition, since the metal interconnections of a related art semiconductor device may be formed according to a predetermined design, it may be difficult to manufacture semiconductor devices that may be required by each individual user.